The present invention relates to a method of manufacturing a wiring board, a method of manufacturing a semiconductor device, and the wiring board, and more particularly to a method of manufacturing a wiring board which is constituted to enhance a reliability of an electrode pad forming portion of a multilayer substrate, a method of manufacturing a semiconductor device, and the wiring board.
For example, as one of methods of forming a BGA (Ball Grid Array) ball to be used for connecting a bare chip to a substrate or connecting a package substrate to a mother board, there has been known a manufacturing method of forming a plurality of electrodes on a substrate, then forming a solder resist having holes communicating with the electrodes, fusing, through a heat treatment (a reflow), a solder ball put on an opening of each of the holes and bonding the solder ball thus fused to the electrode in the hole, and forming a solder bump in a protruding state on a surface of the solder resist.
On the other hand, a package having a bare chip mounted on a multilayer substrate has also been developed with a reduction in a size of the bare chip and an increase in an integration (for example, see Patent Document 1).
FIG. 1 shows an example of a structure of a conventional wiring board. In the structure of the board shown in FIG. 1, layers are arranged in such a manner that an outer periphery of an electrode pad 10 is covered with a first insulating layer 12 and an upper surface of the electrode pad 10 is covered with a second insulating layer 13, and a via 14 extended upward from a center of the upper surface of the electrode pad 10 penetrates through the second insulating layer 13 and is thus connected to a wiring portion 16 in an upper part. The electrode pad 10 has a structure in which an Au layer 17 and an Ni layer 18 are arranged and is provided in such a manner that a surface of the Au layer 17 is exposed from the first insulating layer 12 and the via 14 is connected to the Ni layer 18.
Furthermore, a semiconductor chip is mounted on the electrode pad 10 through a solder bump in some cases, and a solder ball or a pin is bonded to the electrode pad 10 in the other cases. In a wiring board having a multilayer structure, thus, the electrode pad 10 is used as a bare chip loading pad or an external connecting pad.
[Patent Document 1]
Japanese Patent No. 3635219 (JP-A-2000-323613)
In the wiring board shown in FIG. 1, however, the outer periphery of the electrode pad 10 is comparatively smooth. Therefore, an adhesion to the first insulating layer 12 is small. When heating is carried out through a reflow treatment, there is a possibility that a thermal stress might be applied based on a difference in a thermal expansion between the first insulating layer 12 and the electrode pad 10, resulting in the generation of a delamination in a boundary portion provided in contact with the outer periphery of the electrode pad 10 and a breakage of a part of the first insulating layer 12.
In the case in which a part of the first insulating layer 12 provided in contact with an outer periphery of a corner portion (B portion) of the electrode pad 10 is broken off due to heating through the reflow treatment, furthermore, there is a problem in that a crack 20 might be generated from a corner portion (A portion) of the electrode pad 10 toward the second insulating layer 13.
In the case in which the crack 20 is enlarged, moreover, there is a possibility that the wiring portion 16 provided on the second insulating layer 13 might be cut.